Literature Review on Cache Coherence Protocols Shared memory multiprocessors offer the advantage of sharing code and data structures between the processors that make up the parallel application. As a result of sharing, multiple copies of the shared block exist simultaneously in one or more caches. Copies of the shared block existing in different sections must be consistent. This is called cache coherence problem. Various protocols have been designed to ensure hardware consistency, and policies adopted to prevent shared writable data from existing in more than one cache at the same time. Hardware cache coherence protocols include snoopy cache coherence protocols, directory cache coherence protocols, and cache-coherent network architectures. Snoopy cache coherence protocols can be divided into two main categories: Write Invalidate and Write Update. 1.1 Write Invalidate Protocols In Write Invalidate protocols, the processor that modifies a block of shared data invalidates all other copies of that shared data in other caches and then updates its own without additional bus operations. There are four protocols that fall into this category: 1.1.1 Goodman Protocol This protocol was proposed by Goodman in 1983 and was the first write invalidation protocol. It is also known as Write-once protocol. This protocol associates a state with each cached copy of the shared data block. The different states that can be associated with the block are the following:• VALID: The copy of the block is consistent with the copy in memory.• INVALID: T...... half of the sheet......Cache Coherence Protocol2 .3 Chained Directory Cache-Coherence Protocol Keeps track of shared copies of data by maintaining a chain of directory pointers, hence called the Chained Directory Protocol.Fig. Chained Directory Cache Coherence Protocol Suppose there are no shared copies of location X. If processor P1 reads location X, memory sends a copy along with a chain termination (CT) and maintains a pointer to P1. Next, when processor P2 reads location X, memory sends a copy to processor P2's cache along with a pointer to processor P1's cache. If the P3 processor writes to location X, it needs to send a data invalidation message down the chain. To ensure sequential consistency, the memory module denies write permission to the P3 processor until the chain-terminating processor acknowledges the chain invalidation.