C. Issuing Instructions and Parallel Execution Now that the execution tuples are ready, it's time to decide which execution tuple to emit. Ideally, an instruction is ready to execute as soon as its operands are available. In practice, they depend on some constraints such as execution units and registry file ports. Instructions are blocked in the instruction queue until operands are available. Therefore no registry renaming is necessary. It uses a simple reservation bit to indicate instruction completion. The multi-queue method has multiple queues that can issue or order instructions relative to each other. The final method is reservation stations which can issue out-of-order instructions. There is no strict FIFO ordering. These reservation stations do not contain actual data, but contain pointers to the locations of the data.D. Managing Memory Operations Accessing memory is a crucial task. It should be done as quickly as possible. Then memory hierarchies are used, that is, a small and fast memory cache is used. For example, the ARM Cortex A15 processor has 32 KB of data cache and instruction cache. The decoding phase does not identify the memory location that will be accessed. Then you need to calculate the address of the memory to access. This address must be translated to generate the physical address. A translation lookaside buffer is used to speed up this process. There are several methods for incorporating multiple memory operations. But most of them are impractical. The conventional superscalar processor allows if...... half of the paper......me, speed cannot be sustained. As a solution to this, we could use 2-port data cache. Analysis of the results in [3] shows that there was no significant performance improvement when the 2-port data cache was used. So it's a trade-off between cost and performance. REFERENCES[1] James E. Smith, Gurindar S. Sohi “The Microarchitecture of Superscalar Processors”, Proceedings of the IEEE, Volume: 83, Issue: 12, pp. 1609-1624, August 2002.[2] ND Shah, YH Shah, H Modi, "Comprehensive Study of Characteristics, Execution Phases and Microarchitecture of Superscalar Processors", IEEE International Conference on Computational Intelligence and Computer Science Research (ICCIC), pp. 1-4, December 2013.[3 ] Steven Wallace, Nader Bagherzadeh, “Performance Issues of a Superscalar Microprocessor,” International Conference on Parallel Processing, volume: 1, pp. 293-297, August 1994.