Many different approaches are used to reduce power consumption at the circuit design level. Some of the main techniques are transistor sizing, voltage scaling, voltage islands, multiple threshold voltages, and power gating. There is a negative effect with every power optimization technique used at the expense of performance or area. Rabaey (1996) states that the Transistor Sizing (TS) technique is used to adjust the size of each transistor (smallest element in the digital system) or gate (group of transistors) for minimum power at the expense of gate performance. Rabaey also states that the size of the transistor is only changed if its location is not critical and does not affect the performance of the entire circuit. Another technique proposed by Pillai, Shin and Arbor (2001) for power optimization is Real-time Dynamic Volt Scaling (RT-DVS), dedicated to embedded computer systems. The RT-DVS technique exploits the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and operating frequency. Pillai, Shin, and Arbor also show that this RT-DVS algorithm comes very close to the theoretical lower bound of power consumption and can easily reduce power consumption by 20% to 40% in a real-time embedded system. On the other hand the latter will be affected by the reduction of the speed of the whole system when using the voltage scaling technique (Tawfik & Kursun 2009). Another technique called Voltage Island comes to solve the problem of RT-DVS technique where different blocks can be operated at different voltages to save energy in a non-critical island/block (Puri et al. 2005). Puri et al. also show that the voltage island may require the use of level shifters (to change the voltage supply level) when two blocks...... in the center of the sheet ......02). ACM.Puri, R., Kung, D., & Stok, L. (2005, May). Power minimization with flexible voltage islands. In Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (pp. 21-24). IEEE.Tawfik, S.A., & Kursun, V. (2009). Low power, high speed multi-threshold voltage interface circuits. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 17(5), 638-645.Won, H.S., Kim, K.S., Jeong, K.O., Park, K.T., Choi, K.M., & Kong, J.T. (2003, August) . An MTCMOS design methodology and its application to mobile computing. In Low Power Electronics and Design, 2003. ISLPED'03. Proceedings of the 2003 International Symposium (pp. 110-115). IEEE.Weng, S. H., Kuo, Y. M., & Chang, S. C. (2012). Timing optimization in sequential circuits exploiting clock-gating logic. ACM Transactions on Electronic Systems Design Automation (TODAES), 17(2), 16.